1. Field of the Invention
This disclosure relates to analog-to-digital converters, and more particular to analog-to-digital converters using current offsets for reducing power and area requirements.
2. Description of the Related Art
In current-mode analog-to-digital (A/D) converters, reference arrays having a plurality of circuit components or cells may be used to determine a digital output code or A/D output signal from an input analog current I.sub.IN corresponding to input signals. Two techniques may be applied to perform such A/D conversions: bipolar encoding and unipolar encoding.
The current-mode A/D converter 10 shown in FIGS. 1-2 may be used for unipolar coding. Generally, the input current I.sub.IN 12 is switched by cell switches 14 to a unipolar reference array 16 which receives the input current 12 through an input switch 18. The conversion process is controlled by a control circuit 20, known in the art, using control lines 22 to each switch in the A/D converter 10. FIG. 2 shows an example circuit configuration of the current-mode A/D converter 10 for unipolar encoding shown in FIG. 1. For convenience of illustration, the control lines 22 from the control circuit 20 to each switch are not shown in FIG. 2.
The input current I.sub.IN is provided by the input current source 12, which, for example, may be connected to a first voltage node V.sub.1. The cell switches 14 include a plurality of switches 24-28, each respectively associated with one of a set of M cells of the reference array 16. The reference array 16 includes a plurality of current sources 30-34, which may provide substantially equal currents, or which may be weighted. Each of current sources 30-34 is respectively connected to one of the switches 24-28, and each is respectively connected to one of a plurality of current dump switches 36-40 operatively connected to a current dump. In an exemplary embodiment, a first cell includes components 24, 30, 36; a second cell includes components 26, 32, 38; and an M.sup.TH includes components 28, 34, 40.
In processing the input current I.sub.IN, the input current I.sub.IN is compared to a sum of the cell currents associated with each cell of the reference array 16. The reference array 16 includes current sources 30-34 operatively connected to a second voltage node V.sub.2, which may, for example, be connected to ground. The reference array 16 also includes switches 36-40 connected to respective switches 24-28 and to a current dump (not shown in FIG. 2). In such an architecture, the cell currents are adjusted by the control circuit 20 operating switches 24-28 and 36-40 in a manner known in the art to generate an output current. Each cell is connected to a current dump for receiving the current from each respective cell as a respective one of switches 36-40 closes. The processing by the control circuit 20 is performed until a sum associated with the reference array 16, represented by the output current caused by the open and closed switches, is approximately equal to the input current I.sub.IN within the resolution of the A/D converter 10.
A digital output code corresponding to the resulting output current, i.e. the array current value, may be used as the output of the A/D converter 10. In the case where the array cell currents are all equal, the output code may correspond to a count of the number of cells in a predetermined state, such as a "turned on" state.
The accuracy of the above A/D conversion operation may be limited by the accuracy of determination of the array cell currents. For example, a matching of currents in an equally weighted reference array, or the precise ratioing of currents in a non-equally weighted reference array, may be used to determine the integral non-linearity (INL) and differential non-linearity (DNL) of the A/D converter 10. Since a non-equal weighting of array cells may be implemented by grouping cells of an equal-weighted reference array, achieving satisfactory INL and DNL may require the generation of two or more identical reference currents.
In integrated circuit A/D converters fabricated by a process with no post-fabrication trimming, a matching of currents may be obtained for currents of the same polarity. For example, better matching may be possible between the drain currents of two n-channel MOS transistors than between the drain currents of an n-channel MOS and a p-channel MOS device. Accordingly, an input current I.sub.IN of a current-mode A/D may be unipolar to attain improved INL and DNL performance, since the input current I.sub.IN is to be compared to a unipolar reference array.
Generally, input signals such as voice signals may be zero-mean and/or the processing of such input signals may often be idle. Unipolar encoding may be used, but may require an offset current equal to half the total signal swing, which may, in turn, waste power.